1. Field of the Invention
The present invention relates to a phase comparator and a semiconductor device with the phase comparator.
2. Description of the Related Art
A phase locked loop (PLL) circuit comprises a phase comparator for detecting the phase difference between a reference frequency signal and a control target signal, a charge pump whose transistors connected in series are switched on/off by an UP/DOWN signals, respectively, outputted from the phase comparator, a low-pass filter and the like.
Patent Reference 1 discloses that a PLL circuit comprises a pulse width detection circuit for detecting the output pulse width of the frequency phase comparator and the driving capability of a charge pump is increased by connecting two of a p-channel MOS transistor and a n-channel MOS transistor of a charge pump in parallel.
Patent Reference 2 can be obtained by improving Patent Reference 1, and controls its output current characteristic by its phase error signal.
Patent Reference 3 discloses one phase comparator instead of two phase comparators, which can detects the phase difference between two comparison input signals and the output signal by providing a circuit for switching the two comparison input signals.
FIG. 1 shows the simplified circuit diagram of the phase comparator of Patent Reference 3. The circuit of this phase comparator, which generates UP/DOWN signals, is described below.
Comparison target signals A and B are inputted to the clock terminals of type D flip-flops FF1 and FF2, respectively.
The inverted output Q of the type D flip-flop FF1 to which the comparison target signal B is inputted as a clock signal (hereinafter called “output Q bar”) and the output Q bar of the type D flip-flop FF2 are inputted to an OR gate OR1 and its output is inputted to an OR gate OR2. Then, the output of the OR gate OR2 and the output Q of the type D flip-flop FF1 are inputted to an AND gate AND1. The output signal of this AND gate AND1 is outputted as an UP signal for switching a transistor on the power supply side of the charge pump.
The output Q of the type D flip-flop FF2 to which the comparison target signal B is inputted as a clock signal is inputted to an AND gate AND2 and the output signal of the OR gate OR2 is inputted to the other input terminal of the AMD gate AND2. The output signal of this AND gate AND2 is outputted as a DOWN signal for a transistor on the ground side of the charge pump.
If an asynchronous phase comparator for outputting UP/DOWN signals as shown in FIG. 1 is formed on a semiconductor integrated circuit, there is a possibility that an UP/DOWN signal delays due to the wiring length of a logic circuit constituting the phase comparator, a signal that simultaneously switches the two transistors of the charge pump on is outputted, and current flows through the two transistors. If current flows, the leak current of the semiconductor integrated circuit increases.
In the phase comparator shown in FIG. 1, since the comparator target signal A is outputted as an UP signal through the type D flip-flop FF1, two OR gates OR1 and OR2 and an AND gate AND1, and there are many stages of logic circuits, its delay time increases. If the delay time increases in the phase comparator, the detection accuracy of the phase difference degrades and the lock time of the PLL circuit becomes long.    Patent Reference 1: Japanese Patent Application No. H4-241520    Patent Reference 2: Japanese Patent Application No. 2001-7699    Patent Reference 3: Japanese Patent Application No. H3-101517